| IC DFT & Debug Solutions |
| Stridge: At-Speed (AC) DFT, ATPG and Debug |
High coverage AC test patterns increase quality of shipped IC chips. AC DFT strategy is a crucial first step in this direction,
because PLL is active during test. Then comes AC ATPG, logic validation and ATE transfer where the challenge is to unite PLL
behavior in simulation and hardware. ATE execution can become challenging due to Voltage Droop, which will allow delay
defects to escape. Finally, when AC tests fail, their debug is even more challenging because diagnostic tools can’t predict speed
paths on the actual hardware.
Here are our Failure Risk Reduction services through AC testing
because PLL is active during test. Then comes AC ATPG, logic validation and ATE transfer where the challenge is to unite PLL
behavior in simulation and hardware. ATE execution can become challenging due to Voltage Droop, which will allow delay
defects to escape. Finally, when AC tests fail, their debug is even more challenging because diagnostic tools can’t predict speed
paths on the actual hardware.
Here are our Failure Risk Reduction services through AC testing
- AC DFT: Define, implement AC DFT and PLL controls to generate AC clock sequences.
- AC ATPG & Validation: Generate and validate AC ATPG tests, analyze untested faults and generate more tests to meet
production quality levels. Stridge can also generate targeted functional tests if the ATPG tool can’t target the required
critical paths
- Voltage-Droop Strategy: Like Cholesterol, Voltage droop is a silent killer of high speed AC tests. It is also affected by
Process Variations. Stridge will implement proven methods to monitor, detect and resolve voltage droop without affecting
test quality.
- Logic BIST: Logic BIST is the most difficult DFT technique to get working on the silicon. Once working though, it reaps
rewards like no other DFT approach can provide. Lbist can give AC coverage in 90s with few thousand of internal random
patterns, while naturally stimulating critical functional paths.
- Memory BIST: Stridge will devise hardware and/or software BIST algorithms to best fit your Memory Arrays and the types
of faults they can encounter based on design (CAM, ROM, SRAM etc) and the manufacturing process. Stridge can even
Fault Grade Memory BIST algorithms to prove their validity and claim shadow logic test coverage.
- AC Failure Debug: Debugging AC test fails require failure data analysis, scan dumps, STA and logic analysis. Stridge will
leverage its experience debugging most complex game processors to debug your AC test failures.
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