Stridge hires for direct placement on client projects. Work is mostly based in Austin, Texas and very limited travel may be
involved.
Required skills are as follows:
- Candidate must have Ph.D with focus on VLSI Test. OR
- MS degree with at least 3 years experience, OR
- BS degree with at least 5 years of industry experience
- Must be familiar with Verilog/VHDL RTL, know how to navigate through verilog code, simulation waveforms and debug
simulation problems.
- Good fundamental knowledge of DFT basics, test pattern generation, scan testing, 1149.1 JTAG, logic BIST, Memory BIST
algorithms
- Must have prior exposure to either one of these tools: Mentor Graphics (Fastscan); Synopsys (TetraMax); Cadence
(Encounter Test). [Fastscan, TetraMax, Encounter Test are trademarks of their respective corporations]
- Perl scripting is a must.
- C experience is a big plus
- Unix, Linux, AIX, Sun, HP, shell scripting
- Windows word processing, excel, PowerPoint knowledge very useful.
(Note: Candidates please use Contact information to send your resume. Stridge will not accept 3rd party resumes)