| IC DFT & Debug Solutions |
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Design for Test (DFT) is the cornerstone of a good design. Today’s nanometer designs also require Design for Debug (DFD) to be
profitable and to beat the competition. Stridge has expertise managing mission critical challenges in DFT, Memory BIST, Logic
BIST, At-speed (AC) ATPG, ATE debug, and power consumption. From DFT architecture to Silicon Debug, here are Stridge Failure
Risk Management services:
profitable and to beat the competition. Stridge has expertise managing mission critical challenges in DFT, Memory BIST, Logic
BIST, At-speed (AC) ATPG, ATE debug, and power consumption. From DFT architecture to Silicon Debug, here are Stridge Failure
Risk Management services:
- Targeted DFT/DFD Architecture: Stridge will define a DFT/DFD architecture targeted to a chip’s design and its functional
operation. For multi-core chips, Stridge will focus on high quality AC DFT, low power test and debug-ability (DFD).
- SOC/IP DFT/DFD: SOCs and IPs have unique DFT requirements. IP designs are focused on themselves, whereas the SOC
designs want best test quality and lowest price point for an integrated design. Stridge will keep both SOC/IP worlds in focus
to develop a comprehensive DFT/DFD solution.
- Low Power, Reduced Pin-count Test: Burnin, wafer probe, multi-die testing, GHz AC tests require low power consumption
using bare minimum pins. Stridge has experience delivering both for simplest 8-bit microcontrollers and for multi-core
gaming processors.
- ATE Transfer, Failure Debug: Stridge develops Virtual Testers, data translators and performs debug on ATEs like Teradyne,
Agilent, Lab systems etc
- Tools: Stridge will solve your problems using any tool you have. We are well versed in Cadence Encouter Test &
Diagnostics, Synopsys TetraMax and DC/DFTC/Primetime, Mentor Fastscan & Flextest, Waveform debuggers like VCS,
Debussy, Verilog RTL, VHDL, Perl, C, shell.
- Training: Stridge offers continuing education in the following areas:
DFT and Debug Consulting