Stridge Customer Empowerment: Debug Tutorials

Debugging Compression based Tests
Intended Audience
Test engineers, design engineers, researchers and managers for ICs, SOCs, IP cores,
board level and system level silicon debug for chips involving test data compression as
the primary means of testing; those with DFT experience who want to learn about silicon
debug and hence learn Design for Debug (DFD)

Tutorial Summary
More and more ICs are being tested with compression test techniques. Whether using
Logic BIST or targeted compression tools from Mentor, Synopsis, Cadence etc., the
common question is: how to debug a failed signature? This tutorial presents a
comprehensive list of culprits that can cause the actual signatures to mismatch from the
expected ones. Methods to identify and prevent signature mismatches are also
presented.

Above all, this tutorial defines debug terms as applicable to debugging of compressed
test results. For example, in author’s belief, debug is a process that provides complete
resolution for a failure: detect, analyze, locate, fix and log. Note the inclusion of data
logging through which future debug processes, technologies and tools can be improved.
The most important contribution of this tutorial is a complete process and an algorithm to
aid debug of fails in compressed test results.


Tutorial Topics
   Introduction
  1. Debug of Compressed Test Results: Definitions and Overview
  2. Signatures: Calculated, Simulated, Learned signature, Signature Match,
    Unstable signature, Stable signature
  3. Confirmed Operating Signature, Confirmed Device Signature
  4. MISR/Signature-bit masking
  5. Test Channels, Masking, Blocking, Map, Control factor, Balancing
  6. Debug:        Complete resolution of a Fail-Event: detect, diagnose, fix, log

    X Juggernaut: the bane of Test Compression
  1. The X-damage, Extent of Damage, Why is X-debug so difficult?
  2. The knee jerk reaction to Xes: Mask them and move on, Dangerous

    X Sources:
  1. Timing Problems, Voltage Droop, Memory arrays, Dynamic logic
  2. Test Models, Uninitialized Logic

    Debug Xes in Hardware and in Software simulations

   Xes due to Voltage Droop, Xes due to Uninitialized logic

   Debug Data Logs

   Algorithm to debug failures in compressed test results

   Conclusion
  1. Debug is a process
  2. Debug planning and result analysis tools
  3. Hardware and software resources