Stridge Customer Empowerment: SOC/IP DFT and Debug Tutorials
Enhanced JTAG for SOC/IP DFT & Debug
Intended Audience SOC IP providers, SOC integrators, engineers and architects who seek comprehensive Design for Test (DFT) review and enhance their knowledge with Design for Debug (DFD)
Tutorial Summary This tutorial performs a comprehensive review of DFT and DFD for hard IPs and soft IPs. It starts by extending the traditional 2-tier DFT definitions to include reuse, integration and debug of SOC IPs. The attendees will learn about the IC production test flow, CMOS faults, timing faults and DFT techniques for hard and soft IPs.
The most common problem ailing SOC is testing the SOC interconnects with the IP. The tutorial will present a simple test wrapper built by enhancing the common IEEE 1149.1 JTAG standard. Thus the customers can leverage the investment and knowledge they've accumulated in JTAG to solve the current glue logic problems.
Tutorial Topics
Introduction
Basic DFT: Controllability and Observability
SOC DFT: Accessibility, Reusability, Integrate-ability and Debug-ability
Manufacturing Defects, Test Technology and Production Test Flow DFT Process Management: Checklist SOC DFT for Hard-IPs and Soft-IPs SOC Design for Debug: Glue Logic: Logic between SOC core and individual IPs that is not hidden by hard core and which can only be tested after the IP is integrated in the SOC Enhanced JTAG method to test the glue logic
Full IEEE JTAG compliance for board level debug
Observability for SOC core signals coming in
Controllability for IP signals going out to the SOC core
Debug Closure: Progress after problem identification
