Intended Audience Test engineers, design engineers involved with silicon debug of @speed tests.
Tutorial Summary Voltage droop is the invisible, undesirable and unavoidable effect of GHz speeds in nanometer designs. Voltage droop is formed when system speed and circuit speed paths get exclusive engineering attention at the expense of power management. Voltage droop is like cholesterol, a silent killer. Voltage droop can cause test escapes, it is a reliability and quality hazard, and can cause massive field returns.
This tutorial explains the tests and circuit behavior causing the voltage droop. The attendees will learn to detect the presence of voltage droop. Last but not the least, this tutorial shows proven Design for Debug (DFD) methods to prevent voltage droop.
Tutorial Topics
Introduction
What is voltage droop
Common causes of droop
Consequences of voltage droop
Detect Voltage Droop
Eliminate, mitigate voltage droop:
Design for Debug techniques to prevent voltage droop in future designs
